`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:47:09 11/18/2008 
// Design Name: 
// Module Name:    LEDReg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LEDReg(
    input [15:0] Data,
	 input [3:0] push,
	 output reg[15:0] addr,
    output reg [7:0] LED,
	 input reset,
    output Enable,
	 output writeEnable,
    input clk
    );
always@(posedge clk)
if(reset)
LED[7:0] <= 8'b11111111;
else
LED <= Data[7:0];

always@(*)
begin
if(push == 4'b0000)
addr <= 16'h01D1;
else
begin
	addr[15:4] <= 11'b00000000001;
	addr[3:0] <= push;
	end
end 
assign Enable = 1;
assign writeEnable = 0;
endmodule
